1. Field of the Invention
This invention relates to a design layout generating method of forming a design pattern of a semiconductor integrated circuit, and more particularly to the technique for modifying a generated design layout. This invention further relates to a semiconductor device manufacturing method of manufacturing semiconductor integrated circuit devices using the design layout generating method and to a computer-readable medium in which program instructions to be executed on a computer in the design layout generating method has been stored.
2. Description of the Related Art
In the design of semiconductor integrated circuits, it is necessary to conform to the design rules, which are the basic dimension rules for the smallest dimensions, space, shape, and others, determined taking device conditions and process conditions into account. However, even if the design data conforms to the design rules, pattern areas needing modification, for example, process hot spots, might be found as a result of running a process simulation after optical proximity correction (OPC)/resolution enhancement technology (RET) processing is conducted. Specifically, process hot spots include an unexpected spot where patterns make or might make contact with one another or break away or might break away as a result of the pattern width increasing or decreasing in a local part of the patterns, a spot where the line width or space width does not meet predetermined requirements, and a spot where the process margin is below a predetermined value.
A method has already been proposed which works out a table (a design layout change guideline) determining a design layout modification policy by repeatedly modifying at least one of the design rules, the process proximity correction parameter, and the semiconductor process parameter at hot spots and partially modifying the design layout on the basis of the provided design layout change guideline (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. 2005-181524).
There are several methods of partially modifying the design layout. For instance, a method of deriving a pattern satisfying a specified condition by perturbing the edges constituting the pattern (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. 2005-181612). Moreover, another method has been proposed which specifies the amount of modification of the line width or space width on the design layout at a process hot spot, thereby removing the hot spot.
Although the modifying methods are used, it may be impossible to correctly modify all the process hot spots in the input design data. For example, depending on the pattern layout near a process hot spot, the optimum pattern may not be included in the patterns generated by perturbation. Moreover, the amount of modification of the line width/space width may be too large or too small. In addition, a sufficient amount of modification may not be secured at a specified spot because of the limitation of the design rules.
As described above, with the conventional method of determining the amount of modification by reference to a table, the amount of modification may be insufficient/excessive, depending on the pattern. Consequently, the optimum modification may not be made.